1998-2008 CPES Strategic Plan

9 September 1998 Draft

1.0 Vision 1.1

Vision Statement
CPES will provide the nation with the capabilities to become a world leader in power electronics through a multi-disciplinary, multi-university, and multi-industrial partner program extending over a ten year period. The program will be based on an integrated systems approach to standardize power electronics components and packaging techniques in the form of highly Integrated Power Electronics Modules (IPEMs). The IPEM approach makes possible increased levels of integration in the components that comprise a power electronic system - devices, circuits, controls, sensors, and actuators. These components are integrated into standardized manufacturable subassemblies and modules which, in turn, are customized for particular applications.

The range of applications is very broad, spanning both commercial and military industrial sectors that have been identified by the Office of Science and Technology Policy as critical to the growth of the U.S. economy. These sectors include energy efficiency improvement; energy storage, conditioning, distribution and transmission; pollution avoidance, remediation and control; communications; computer systems; propulsion and electronic power for transportation; and system integration. Today, the power electronics market worldwide is estimated to be $30 B in direct product sales, and it supports an additional $570B in hardware electronics industries.

The Center has four primary goals:

1. Enable a 10-fold improvements in the quality, reliability, cost effectiveness and design cycle time of IPEMs.
2. Demonstrate developed system integration concepts and technology transfer in three Demonstrative programs: distributed power systems (e.g. for computers), high performance drives and HVAC packaged drives
3. Train future technical leaders by developing innovative power electronics system-oriented curricula and approaches to foster inter-disciplinary learning.
4. Deploy the knowledge gained by CPES initiatives through active outreach programs and industrial affiliate programs.

1.2 State of the Art

1.2.1 Power Electronic Components

Over the past 10 years, the power device industry has undergone a revolutionary change, from bipolar technology-based devices to MOS technology-based devices. This change has allowed the alignment of power device manufacturing technology with the IC technology used to fabricate CMOS devices (memory and microprocessor chips). High voltage integrated circuits (HVICs) that combine CMOS digital interface circuits, bipolar analog control circuits, and high voltage drive transistors have also been developed for applications such as power supplies and adjustable speed motor controls. These HVICs have enabled the level-shift function and have allowed the low cost integration of sensing and protection features. The combination of MOS-gated power switches and HVIC control chips has led to the evolution of the intelligent power module manufactured by foreign companies. Unfortunately, a comparable technology has not yet been commercially introduced by domestic manufacturers.

1.2.2 Power Electronics Circuits and Packaging

Circuit assembly and packaging technologies for (high) power electronics have not kept pace with those of low-power electronics. Power electronics equipment is mostly custom-designed and requires a labor-intensive manufacturing process. The resulting products are usually characterized by poor quality, low reliability, long design cycles, and high cost.. Again, foreign competitors have taken a more aggressive approach in recent years, developing a high level of integration. For example, in a power inverter for an adjustable speed drive, all the power semiconductors are mounted on a common substrate in die form. The associated drivers, protection, and sensors are realized in the form of a high-density printed circuit board, using surface-mount components, and packaged inside the plastic enclosure, together with the power devices. Monolithic integration of power electronics devices ((on a single chip to simplify assembly and packaging) generally has not been cost-effective and has been limited to low power applications.

1.2.3 Distributed Power Systems (DPS)

Centralized power electronics equipment is currently used in most applications. However, recently the DPS approach has been gaining rapid acceptance. The benefits of DPS are flexibility, point-of-load regulation with precise control, the ability to integrate the converter and actuator, increased reliability through redundancy, standard designs for parallel operations requiring high current and high voltage, and short design cycles resulting from a modular approach. Examples of applications particularly suited to DPS are: a) main frame computers requiring high current supplies, b) high speed processors (from 200MHz to 1GHz and beyond) with stringent requirements for voltage regulation resulting from distributed impedances and parasitic high frequency ringing associated with long power bus lines c) processors operating at ever lower logic voltage (down to 1.2V) requiring novel power management and regulation, d) aircraft "fly-by-wire" (versus hydraulics) control systems, and e) automobile electrical systems which would otherwise require increasingly bulky wiring harnesses as the electronics become ever more sophisticated.

1.2.4 Education

Under the present U.S. educational system, the younger generation of electrical engineers are inadequately prepared to deal with the complex design tradeoffs required to optimize a power electronics system. Within the discipline of electrical engineering, power electronics technologies cut across a wide spectrum of specialties, such as semiconductor materials and devices, analog and digital electronic circuits, communication, control, electric machines, power generation, conversion, distribution, and numerous application considerations. Furthermore, design of a power electronics system requires extensive knowledge of non-traditional electrical engineering disciplines, such as electromechanical actuators, engines and generators, advanced materials for packaging, and thermal management. Although each of these areas is addressed in our various engineering disciplines, their interrelationship at the system level has not been established in our curricula]. Consequently, more than 90 percent of the practicing engineers in the power electronics industry must be trained on the job.

1.3 Barriers and Gaps

The task of developing IPEM components and processes suitable for standard use in customized power electronics applications must overcome numerous barriers which are, in general, more complex than those faced in the development of low power VLSI circuits. These barriers/gaps fall into four major categories:

:Devices: a) limited availability of stable of high current injection devices, b) lack of large-area low defect density SiC, GaN, and AlN wafers for high temperature and higher efficiency power devices, c) conflicting materials and processes requirements in monolithic integration of high-voltage (and high current) devices for power and low-voltage (and low current) devices for controls and sensors

Packaging: a) difficulty in interconnecting high-power devices and control devices on a common substrate in hybrid assemblies while maintaining reliability, optimal thermal management, and minimal cross- talk (arising from strong EM fields), b) parasitic capacitance and inductance in three-dimensional device packaging, c) bulky high-power passive devices which are unsuitable for integration with active power devices into small packages, d) potentially strong interactions between the tightly coupled non-linear IPEM subsystems over a wide frequency range

Systems: a) lack of some form of standardization for the architecture of DPSs, b) non-uniform or non-existent methodology of implementing various features such as modularity, redundancy, fault tolerance, and serviceability c) unavailability of a system -level approach to provide the needed interface requirement for suppressing unwanted interactions among various equipment. d) system level monitoring, command, control and communication protocols not yet established and adopted by industry. e) lack of a methodology to integrate the many software packages used in power electronic component and system design, and f) lack of a comprehensive cost model to assess the cost impact of advanced components at the systems level

Industry: a) lack of vertical integration in U.S. corporations leading to a barrier to systems optimization because the components are developed in isolation (Conversely many foreign companies are vertically integrated, giving them a competitive advantage.), b) no formal mechanism in place to capture and track the necessary component and system specifications in a manner that will ensure success.

1.4 Why a Center is Needed

There are several universities, industries and government programs aimed at improvements in Power Electronics. However, as pointed out above, the task of putting the U.S. into a leadership position is highly complex, and no single entity has sufficient resources, knowledge and experience to address the task comprehensively. Accordingly, the only viable approach is to assemble a broad-based coalition comprised of Government (NSF), Academia and Industry.

Virginia Tech and University of Wisconsin host the two largest university/industry collegiate programs in the field of power electronics. The current research programs at the five universities affiliated with CPES are directed toward specific research areas relevant to the Center's goals. At Virginia Tech, research is focused on high-frequency power conversion devices and circuit technologies, power electronic packaging, and systems integration. Research at the University of Wisconsin is focused on industrial and utility-grade power conversion, electric machines and motor drives, and industrial controls. At RPI, research is focused on novel discrete power semiconductor materials, process techniques, power devices, and smart power ICs. At North Carolina A&T State University, research is focused on nonlinear control, neural networks, and fuzzy logic-based intelligent control. At the University of Puerto Rico, Mayaguez, research is focused on non-linear controls and their application to drives. Thus, CPES, with its extensive resources and established industrial collaboration programs, will be able to significantly leverage NSF support to accomplish this strategic plan.

1.5 Engineered Systems - Demonstrative Programs

There are three Demonstrative programs, each consisting of four separate Generations as illustrated in Figure 1. Each testbed will be developed and demonstrated at the appropriate university to establish proof-of-concept. In parallel, but lagging slightly in time, a selected Industry will build a similar test bed to evaluate the manufacturability and cost aspects of each generation. The other key milestones in the figure are discussed in the Research Strategy section.

1.5.1 Demonstration Thrust 1: Distributed Power Systems (DPS)

A distributed power system testbed typifying a high-end server and workstation will be developed. This testbed will also be applicable to telecommunication DPS equipment which will be operated at a somewhat higher power level but with the same power architecture. The DPS consists of a front-end processor which will convert the utility power into a regulated 48v bus. It is featured with excellent utility interface (high power factor and low harmonic distortion), to allow different power requirements to be met by the simple paralleling of these modules. The processor will be developed with a high level of integration using IPEM-based modular approach to provide flexibility to scale up/down and redundancy.

The load converters modules will convert the 48v bus voltage to various forms of voltages necessary. The load converter will be developed with a strong emphasis on low-cost, high-efficiency, low-profile, high-power density. This is critical to support and future generation of processors. The traditional centralized power supplies cannot meet the stringent requirements for voltage regulation because of the distributed impedances associated with long power bus and the parasitic ringings due to high-frequency operation. A voltage regulator module (VRM) must be used to provide the needed power to the processor chip and to regulate its voltage under load transients. As the future logic voltage continues to decrease from 3.3 V to 1.5 V and the clock frequency increases beyond 1 GHz, new approaches to power management and regulation must be developed in order to meet even more stringent requirements. We will attempt to develop an integrated power IC using SOI LDDMOS to increase the operating frequency from hundreds of kilohertz into megahertz in order to reduce the size and weight of energy storage elements.

1.5.2 Demonstration Thrust 2: High Performance Drives (HPD)

In this demonstration thrust we will integrate some of the key advances in increasing levels of integration that have already been made at the five participating institutions. This demo will feature IPEMs based on conventional devices, such as IGBTs, as well as power devices fabricated with advanced materials such as SiC. The work will also focus on the possibility of configuring a "custom motor drive" based on the IPEM concept, using a flexible manufacturing systems approach. This drive will be based on an advanced device type and will feature an integrated controller on a custom chip. The controller will be programmable to fit functional specifications for the targeted application. The ultimate aim is to bring about a ten-fold improvement in performance and cost. Allen-Bradley, a leading company in high performance AC drive manufacturing, has agreed to serve as an industrial testbed. The HPD will be developed at U of W and tested at NC A&T. Motorola and Harris, the two leading power semiconductor manufacturers in the nation, will serve as our testbed partners in supporting the device development effort.

1.5.3 Demonstration Thrust 3: Packaged Drives (PD) for Heating, Ventilation, and Air-Conditioning (HVAC)

In this thrust we will develop a cost-effective, reliable, general purpose packaged adjustable speed drive which will utilize a versatile, smart, and robust controller, such as a neural-controller or a fuzzy logic controller. The goal is to improve energy efficiency, comfort, and other "subjective" performance measures. We will verify and demonstrate the improvements in cost, efficiency, reliability and performance for a wide range of applications. The HVAC system will be used as an application vehicle for the first two generations of the testbeds because of its vast market potential and significant energy savings. As the cost of PDs is reduced, with the development of high-temperature SiC-based IPEMs, other emerging applications having significant economic and environmental impacts, such as electric vehicles and hybrid electric vehicles, will be considered for Generation-III and Generation-IV testbeds. The PDs will be developed at Uof W, with industry support from York International, GM, and Harris.

2.0 Research Strategy

2.1 Research, Testbeds, Milestones

The key elements of the Research program are depicted over time in Figure 1. It is anticipated that there will be four Research Phases and four respective generations of testbeds, leading to an overall improvement of 10X (Benchmarks) over the life of the program.

2.2 Summary of Research Program

Key Milestones

Table 2 provides a milestone chart summarizing the proposed CPES programs. The Research Program is divided into four different phases over ten years. The milestone chart indicates that technology advances in materials, power devices, IPEMs, packaging, and their system implementations are projected into each of the four generation testbeds. Phase I will utilize state-of-the-art components and packaging techniques to produce planar power packages on high performance ceramics. Conventional first-level interconnections from component to package, such as wirebonds and reflow solders, will be utilized. The integration of passive components into the substrate base will be limited to resistors and small capacitance values. Efforts will be made to develop an integrated design approach based on commercially available CAD tools in order to produce component and interconnection layouts with minimum parasitics and proper thermal management. These initial efforts are intended to stretch the boundaries of current technologies to achieve optimal performance. The first generation of IPEMs will be implemented in the demonstrative programs and testbeds. This phase will also serve as a baseline for future efforts. Since the technologies and processes employed in the Generation-I Testbed is relatively known, the duration of Phase I of the program is only one and a half years.

In Phase II, second-generation IPEMs will be developed using advances made in silicon devices and SiC Schottky diode, and integrated passive components. Multilayer ceramics and organic laminates, as well as multilayer deposited technologies, will be used to extend the multichip-module (MCM) technologies to higher power applications. This extension will be accomplished by integrating passive components into buried layers of the substrate, and by using unpackaged components on a multilayer substrate base which incorporates all of the electronic interconnections. Both control and power circuitry will be incorporated into the same substrate whenever possible. Particular attention will be given to thermal management through the use of advanced ceramic and/or metal matrix composites (MMCs). The second-generation testbeds will enable quantitative evaluation of progress made in CPES in terms of advances in power electronics systems performance. The projected performance in terms of improvement and cost reduction is to be at least double that of the first generation. Phase II will be performed in a period of three and a half years.

Phase III begins in Year 6. Research in SiC materials conducted in Phase I and Phase II will become mature and can be implemented into the third generation testbed. High-temperature SiC-based IPEMs will be developed. The work will also focus on the development of improved multilayer materials with increased thermal conductivity. Materials and processing technologies will be developed to allow greater thermal conductivity. Ferrite tapes and pastes, as well as high performance ceramics, such as Aluminum Nitride and Silicon Carbide, will be investigated for use in power modules. The goal this phase will be to improve the thermal properties of power modules and to integrate as many of the passive components into the substrates as possible. With the high temperature capability using SiC, we expect significant improvement in performance, size, weight, and cost by a factor of 4. The applications of IPEMs and systems integration will be extended to applications such as automotive electronics, where high temperatures are required.

In the Final Phase of this project which begins in Year 8, other advanced semiconductor devices such as III-N-based IPEMs will be developed. All of the advanced techniques and materials developed previously will be combined into a fully-integrated 3-dimensional Multichip Power Module in order to realize a tenfold improvement in performance and cost.

2.3 Integration of Research Areas

Figure 2 illustrates how we are pooling the resources and expertise of five Universities to accomplish the Research Program outlined above.

A multi-university program presents special challenges in managing the flow of research. Figure 3, "University Partner Research Flow", depicts the Key Research Program Elements, Universities primarily responsible for each Element, and how the Output of each Element becomes an Input to the other Elements of the program. The research output can either be Direct ( provide an approach, component or subsystem) or it can provide Requiremens (specifications, needed modifications, additional research). As can be seen, the program is highly integrated with extensive interaction among all the participants and program elements.

2.4 Resources

The research programs at the five universities are quite complementary, with faculty expertise covering all essential disciplines necessary for the proposed work. Some degree of overlapping in research interests and expertise exists among the five institutions, making it feasible for the team to work together despite the geographical separation. Figure 4 shows the primary responsibility for the four Technology Development areas and the three Demonstrative Program Testbeds.

3.0 Education strategy

In the Education Program, a comprehensive power electronics system-oriented curriculum will be developed to include new courses in the area of power electronics packaging, system design and integration, and relevant courses already in existence. A total of sixty-two existing courses and thirteen new courses will be cross-listed for all five universities to strengthen their undergraduate, M.S., and Ph.D. programs. Exchange programs for faculty and students will be implemented to facilitate the integration of the curriculum. An undergraduate curriculum with a power electronics option will be offered at Virginia Tech, UW, and RPI within the first two years. A Ph.D. program in power electronics with NC A&T will be established in the third year and with UPR in the fifth year. Fifty M.S. students are currently enrolled in the five universities. The number of M.S. students is expected to grow to 150 by the end of the fifth year. The number of Ph.D. students is expected to grow from 65 to over 125. Undergraduate students involved in research in various challenge programs are expected to grow from 100 to over 300 students.

The Outreach activities will take place within the Research, Education, and Industrial Collaboration programs. The Center has budgeted thirty-eight fellowships and scholarships annually to offer the opportunities for firsthand experience in CPES's education and research initiatives. Included in this program are six (6) fellowships for the graduate student visitor program, three (3) visiting faculty/post-doctoral fellowships, nine (9) fellowships for underrepresented populations, ten (10) scholarships for the Summer Undergraduate Research Experience (SURE) program, and ten (10) fellowships for high-school summer camps. The latter program will be offered by the five universities on the rotational basis. CPES has also committed to provide continuing education opportunities for practicing engineers. Seventeen short courses currently offered will be updated to include new research results developed under CPES research. Total enrollment from industry in these short courses is expected to grow from 200 to over 400 by the third year. Distance learning is currently offered through NTU and video. CPES's educational programs and research results will be made available through the Internet. We expect to reach out to more than 1000 engineers per year.

4.0 Industrial Interaction Strategy

The Industrial Collaboration between industries and the five participating universities will take place through several avenues, including joint research and demonstration projects, university/industry exchange program, and industry participation on the CPES's education, research, and technology transfer missions. The CPES Industrial Consortium will offer two levels of memberships -- Associate Member and Principal Member. Eighty-three Associate and 15 Principal Members have already been recruited. We expect the membership for Principal Members to grow to 30 by the third year and to 40 by the fifth year. Principal Members will participate in CPES research and serve as industry testbeds for the three demonstrative programs. Industrial personnel participating in the Industry Residence Program is expected to grow annually from 10 to 30 in five years, and the Graduate Industry Internship Program is expected to grow annually from 20 to 40 in the same time frame.